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NATIONAL WORKSHOP On Xilinx Vivado Design For Signal And Image Processing Using Hardware Co-Simulation In Zynq SoC

Event Name


Event Type



Erode, Tamil Nadu (TN)

Event Date(s)

11 Jul 2019 - 12 Jul 2019

Who Can Participate

Common For All

Institution Name

Kongu Engineering College


Registration Details

Registration Date(s)

01 Jun 2019 - 05 Jul 2019

Spot Registration


Registration Procedure

The applicants should send their applications in the specified format to reach us on or before 05.07.2019. If selected, they should confirm their participation in time.

Event Details

Event Details

Introduction to Xilinx
Introduction to 7 series FPGA, Architecture and Zynq SoC
Zynq PS Flow & Adding IP Core in PL
Extending the hardware design by adding AXI Peripheral using IP catalog
Creating and adding your own custom Peripheral IP.
PMOD WIFI Interfacing Using Zynq SoC
Monitoring on-Chip Temp Sensor using Zynq SoC.
Introduction to Xilinx System Generator
Gray scale Image Enhancement and Median Filter Design and its verification by Hardware Co-Simulation on Zynq SoC

Event Website

Event Location

Institution Name

Kongu Engineering College

Website link


Erode, Tamil Nadu (TN), India


Department of EEE,
Kongu Engineering College,
Perundurai, Erode-638 060, TamilNadu
Contact Mobile–9443350335

Event Contact Details

Contact Email



Additional Details

Organizer Details

Mr. S.K.Logesh, M.E.,
Assistant Professor/EEE
Xilinx Vivado Design for Signal & Image Processing using Hardware Co-Simulation in Zynq SoC
Department of EEE,
Kongu Engineering College,
Perundurai, Erode-638 060, TamilNadu
Contact Mobile–9443350335,

Event Submitted By


Last Updated On

2019-06-19 11:46:05

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